1. Field of the Invention
The present invention relates to a high-speed and high-precision sample-and-hold circuit device comprising a MOS analog switch.
2. Description of the Invention
According to a conventional sample-and-hold circuit device, a MOS analog switch samples an input analog signal and a voltage of the input analog signal is held in a capacitor. When the MOS analog switch is set in a closed state, the input analog signal is sampled and charge is accumulated in a capacitor until a terminal potential of the capacitor reaches an input terminal potential. Then, the MOS analog switch is set in an open state, the input terminal is separated from the terminal of the capacitor, and the charges accumulated in the capacitor are held.
In the conventional sample-and-hold circuit device, when the MOS analog switch is operated at high speed, i.e. the frequency for switching the MOS analog switch is increased, it is difficult for the conventional sample-and-hold circuit to perform an ideal sample-and-hold operation. The reason for this will be described below.
Stray capacitance called overlap capacitances are present between a gate electrode and a drain electrode and between the gate electrode and a source of each MOS transistor. When the MOS switch is changed from the closed state to the open state by a control signal supplied to the gate electrode, the control signal leaks from the gate electrode into the capacitor through the overlap capacitor. The leaking signals represent an error charge and are superposed on the charges held in the capacitor.
In addition, according to an operational principle of a MOS transistor, channel changes are generated in the channel of the MOS transistor during the ON state. When the MOS transistor switches to an OFF state at a very low speed, the channel charge flows in the one of the source and drain electrodes which has a lower impedance. In contrast to this, if the MOS transistor goes to an OFF state at a high speed, the channel charge branches and flows in both the source and drain electrodes. Therefore, if the sampling rate is increased, a given percentage of channel charge is superposed, as error charge, on the charges held in the capacitor.
In using an MOS transistor as a sampling switch for the conventional sample-and-hold circuit, a p-channel MOS transistor and an n-channel MOS transistor are connected in parallel with each other i.e, a CMOS transistor switch,.so as to reduce the variation of the CMOS transistor's resistance corresponding to voltage of the input signal. The channel charges of the p-channel MOS transistor and those of the n-channel MOS transistor have electrical characteristics opposite to each other, so the CMOS transistor switch decreases the amount of error changes caused by the two kinds of channel charges.
However, the amount of channel charge relative to the voltage of the input signal is different among the respective transistors. Moreover the amount of the channel charge of the p-channel MOS transistor is not equal to the charge of the n-channel MOS transistors, and the error charge of each transistor is not compensated exactly in the way described above. The amount of error charge which is not compensated completely and remains as channel charge is dependent on input voltage, which is called the non-linear characteristic error, so this characteristic causes a non-linear error of the output voltage relative to the input voltage.
In another way to cancel error charges, error-cancelling p-channel MOS and n-channel MOS transistors are connected in parallel to a terminal of sampling p-channel MOS transistor and sampling n-channel MOS transistor to construct CMOS transistor as a sampling switch. The error-cancelling transistors are set to ON and OFF states complimentarily to the CMOS transistor. Then the error charges of the sampling p-channel MOS transistor and the sampling n-channel MOS transistor flows into the error-cancelling p-channel transistor and the error-cancelling n-channel transistor, because when those sampling transistors are set in the OFF state, these error-cancelling transistors are set in the ON state. As a result, ideally, the error charges are not held in the capacitor.
However, in practice, the two transistors for switching are not set in ON state at the same time. It is quite difficult to synchronize the switching transistors during the ON state. Then, the error charge of one sampling transistor which is set in the OFF state earlier flows in the side of the input terminal through the other sampling transistor which is still set in the ON state, and the error charge is not cancelled completely.
As described above, in the conventional technique, the error charge caused by the stray capacitance of the MOS transistor and by the channel charge in the channel of the MOS transistor can not be cancelled perfectly. So the voltage held in the capacitor is different from the voltage of the input signal.